// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// PROGRAM		"Quartus II 32-bit"
// VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version"
// CREATED		"Fri May 17 09:57:54 2013"

module DDS_V1(
	WR,
	RD,
	CS0,
	nCFG,
	CLK_25M,
	AB,
	DA_CLK,
	DA_DB,
	DB
);


input wire	WR;
input wire	RD;
input wire	CS0;
input wire	nCFG;
input wire	CLK_25M;
input wire	[18:16] AB;
output wire	DA_CLK;
output wire	[15:0] DA_DB;
inout wire	[15:0] DB;

wire	dds_ctl_clk;
wire	[15:0] SYNTHESIZED_WIRE_0;
wire	[15:0] SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	[11:0] SYNTHESIZED_WIRE_4;
wire	[15:0] SYNTHESIZED_WIRE_5;

assign	DA_CLK = SYNTHESIZED_WIRE_3;




DDS_CTL	b2v_inst(
	.CLK(dds_ctl_clk),
	.RSTn(nCFG),
	.CS(CS0),
	.WRn(WR),
	.RDn(RD),
	.RS(AB[16]),
	.CMDIN(SYNTHESIZED_WIRE_0),
	.DATIN(SYNTHESIZED_WIRE_1),
	.RAM_WEN(SYNTHESIZED_WIRE_2),
	.RAM_CLK(SYNTHESIZED_WIRE_3),
	.RAM_ADDR(SYNTHESIZED_WIRE_4),
	.RAM_DAT(SYNTHESIZED_WIRE_5));
	defparam	b2v_inst.DDS_DISABLE = 16'b0000000000000000;
	defparam	b2v_inst.DDS_ENABLE = 16'b0000000000000001;
	defparam	b2v_inst.DDS_PAUSE = 16'b0000000000000010;
	defparam	b2v_inst.DDS_RESET = 16'b0000000000000011;
	defparam	b2v_inst.RAM_ADDR_WID = 8'b00001100;
	defparam	b2v_inst.RAM_DATA_WID = 8'b00010000;
	defparam	b2v_inst.SET_ADDR = 16'b0000000000000111;
	defparam	b2v_inst.SET_BUF_SIZE = 16'b0000000000000100;
	defparam	b2v_inst.SET_FRE_PARA = 16'b0000000000001010;
	defparam	b2v_inst.SET_FRE_PARA_H16B = 16'b0000000000001101;
	defparam	b2v_inst.SET_FRE_PARA_L16B = 16'b0000000000001100;
	defparam	b2v_inst.SET_NONE = 16'b0000000000001011;
	defparam	b2v_inst.WR_FULL_DAT = 16'b0000000000000101;
	defparam	b2v_inst.WR_ONE_BYTE = 16'b0000000000001000;
	defparam	b2v_inst.WR_TO_RAM = 16'b0000000000000110;


PLL	b2v_inst2(
	.inclk0(CLK_25M),
	
	.c0(dds_ctl_clk)
	
	
	);


FSMC	b2v_inst3(
	.wrn(WR),
	.rdn(RD),
	.resetn(nCFG),
	.csn(CS0),
	.ab(AB),
	.db(DB),
	
	
	
	
	
	
	
	
	
	.outa(SYNTHESIZED_WIRE_0),
	.outb(SYNTHESIZED_WIRE_1)
	
	
	
	
	
	);


DDS_RAM	b2v_inst5(
	.wren(SYNTHESIZED_WIRE_2),
	.clock(SYNTHESIZED_WIRE_3),
	.address(SYNTHESIZED_WIRE_4),
	.data(SYNTHESIZED_WIRE_5),
	.q(DA_DB));


endmodule
